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MITSUBISHI LSIs
M5M5V4R04J-12,-15
1997.11.20 Rev.F
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
DESCRIPTION The M5M5V4R04J is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. The M5M5V4R04J is offered in a 32-pin plastic small outline Jlead package(SOJ). These device operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. PIN CONFIGURATION (TOP VIEW)
FEATURES
M5M5V4R04J-12 **** 12ns(max) M5M5V4R04J-15 **** 15ns(max) * Low power dissipation Active ********** 297mW(typ) Stand by ******* 3.3mW(typ) * Single +3.3V power supply * Fully static operation : No clocks, No refresh * Common data I/O * Easy memory expansion by S * Three-state outputs : OR-tie capability * OE prevents data contention in the I/O bus * Directly TTL compatible : All inputs and outputs * Fast access time
A0 A1 address A2 inputs A3 A4 chip select S input data inputs/ DQ1 outputs(3.3V) VCC (0V) GND data inputs/ DQ2 outputs write control W input A5 A6 address A7 inputs A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A19 A18 address A17 inputs A16 A15 output enable OE input DQ4 data inputs/ GND (0V) outputs VCC (3.3V) DQ3 data inputs/ outputs A14 A13 address A12 inputs A11 A10 NC
M5M5V4R04J
Outline
32P0K(SOJ)
APPLICATION High-speed memory units BLOCK DIAGRAM
A0 A1 A2
address inputs
PACKAGE 32pin 400mil SOJ
ROW ADDRESS DECODERS
1
ROW INPUT BUFFERS
7
OUTPUT BUFFERS
DQ1 DQ2 DQ3 DQ4
data inputs/ outputs
2 3 4
10 23 26
A3
A4 5 A5 12 A6 13 A7 14 A8 15
MEMORY ARRAY 512 ROWS 8192 COLUMNS
S
6
COLUMN I/O CIRCUITS COLUMN COLUMN ADDRESS DECODERS ADDRESS DECODERS COLUMN INPUT BUFFERS
DATA INPUT BUFFERS
8 24 9 25
W
11
VCC (3.3V)
OE 27
GND (0V)
16 18 19 20 21 22 28 29 30 31 32 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
address inputs
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V4R04J is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time.
FUNCTION TABLE
S H L L L W X L H H OE X X L H Mode Non selection Write Read DQ High-impedance Din Dout High-impedance Icc Stand by Active Active Active
ABSOLUTE MAXIMUM RATINGS
Symbol V cc VI VO Pd Topr T stg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Ta=25 C With respect to GND Conditions
*
Ratings -2.0 ~ 4.6 -2.0 ~ VCC+0.5 -2.0 ~ VCC+0.5 1000 0 ~ 70 -10 ~ 85 -65 ~ 150
+10% -5%
* *
Unit V V V mW C C C
Tstg(bias) Storage temperature (bias) Storage temperature
*Pulse width 20ns, In case of DC:-0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V
Symbol VIH VIL VOH VOL II I OZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Condition
unless otherwise noted) Limits Min 2.0 -0.3 2.4 Typ Max Vcc+0.3 0.8 0.4 2 10 Unit V V V V A A
IOH =-4mA IOL= 8mA V I = 0~Vcc VI (S)= VIH Output current in off-state VO= 0~Vcc Active supply current (TTL level) VI (S)= VIL other inputs V IH or VIL Output-open(duty 100%) 12ns cycle AC DC 12ns cycle AC DC 15ns cycle 15ns cycle
160 150 90 100 75 70 50 1 10 mA mA mA
I CC1
I CC2
Stand by current (TTL level)
VI (S)= VIH VI (S)= Vcc0.2V other inputs VI0.2V or VIVcc-0.2V
I CC3
Stand by current
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M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0 ~ 70 C, Vcc=3.3V
Symbol CI CO Parameter Input capacitance Output capacitance
+10% -5%
unless otherwise noted) Test Condition Limit Typ Unit pF pF
Min
Max 7 8
V I =GND, V I =25mVrms,f=1MHz V O=GND, VO=25mVrms,f=1MHz
Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc=5V,Ta=25 C 3: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (1)MEASUREMENT CONDITION
(Ta=0 ~ 70 C, Vcc=3.3V
+10% -5%
unless otherwise noted)
Input pulse levels ************************ V IH =3.0V, V IL =0.0V Input rise and fall time ************************************** 3ns Input timing reference levels ************ V IH =1.5V, V IL=1.5V Output timing reference levels ********** V OH=1.5V, V OL =1.5V Output loads ****************************************** Fig1 ,Fig2
Vcc OUTPUT Z0=50 DQ RL=50 VL=1.5V 255 480 5pF (including scope and JIG)
Fig.1 Output load
Fig.2 Output load for t en, t
dis
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(2)READ CYCLE
Limits
Symbol Parameter
M5M5V4R04J -12 Min Max
M5M5V4R04J -15 Min 15 Max
Unit
tCR ta(A) ta(S) ta (OE) tdis(S) tdis (OE) ten(S) ten (OE) tv(A) tPU tPD
Read cycle time Address access time Chip select access time Output enable access time Output disable time after S high Output disable time after OE high Output enable time after S low Output enable time after OE low Data valid time after address change Power-up time after chip selection Power-down time after chip selection
12 12 12 6 0 0 0 0 3 0 12 6 6
ns 15 15 8 ns ns ns ns ns ns ns ns ns 15 ns
0 0 0 0 3 0
7 7
(3)WRITE CYCLE
Limits
Symbol Parameter
M5M5V4R04J -12 Min Max
M5M5V4R04J -15 Min 15 12 0 0 12 7 0 1 Max
Unit
t CW tw(W) tsu(A)1 tsu(A)2 tsu (S) tsu (D) th(D) trec(W) tdis (W) tdis (OE) ten (W) ten (OE) tsu(A-WH)
Write cycle time Write pulse width Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Address to W High
12 10 0 0 10 6 0 1 0 0 0 0 10 6 6
ns ns ns ns ns ns ns ns 7 7 ns ns ns ns ns
0 0 0 0 12
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M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle 1 A 0~19
VIH VIL
t CR
ta (A) tv (A) tv (A)
UNKNOWN DATA VALID PREVIOUS DATA VALID
DQ1~4
VOH VOL W=H S=L OE=L
Read cycle 2 (Note 4)
t CR
S
VIH VIL
ta(S) ten(S)
(Note 5)
tdis(S)
(Note 5)
DQ1~4
VOH VOL
UNKNOWN
DATA VALID
tPU
tPD
50% 50%
Icc
ICC1 ICC2 W=H OE=L
Note 4. Addresses valid prior to or coincident with S transition low. 5. Transition is measured 500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6) OE
VIH VIL
t CR
ta (OE)
(Note 5)
tdis(OE)
(Note 5)
ten(OE)
UNKNOWN DATA VALID
DQ1~4
VOH VOL W=H S=L
Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
Write cycle ( W control mode )
t CW
A 0~19 S
VIH VIL VIH VIL (Note7)
tsu(S)
(Note7)
tsu (A-WH)
OE
VIH VIL
tsu (A)
tw(W)
trec (W)
W
VIH VIL
tsu (D) th(D)
DQ1~4
(Input Data)
VIH VIL
DATA STABLE
tdis(W) (Note 5) tdis(OE)
ten(OE) (Note 5) ten(W)
DQ1~4
(Output Data)
VOH VOL Hi-Z
Write cycle (S control mode )
t CW
A 0~19
VIH VIL
tsu(A)
VIH
tsu (S)
trec(W)
S
VIL
tw(W)
VIH
W
VIL (Note7) (Note7)
tsu (D)
th (D)
DQ1~4
(Input Data)
VIH VIL
DATA STABLE
tdis(W) ten (S)
(Note5)
DQ1~4
(Output Data)
VOH VOL
(Note5)
Hi-Z
(Note8)
Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: ten,tdis are periodically sampled and are not 100% tested.
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